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  <title>Intel处理器架构简介 | 惘客的个人博客</title>
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        <h2 id="CPU-工作模式"><a href="#CPU-工作模式" class="headerlink" title="CPU 工作模式"></a>CPU 工作模式</h2><h3 id="IA-32-架构"><a href="#IA-32-架构" class="headerlink" title="IA-32 架构"></a>IA-32 架构</h3><p>即通常说的 x86 架构，该架构下存在以下几种工作模式：</p>
<h4 id="Real-address-mode"><a href="#Real-address-mode" class="headerlink" title="Real-address mode"></a>Real-address mode</h4><p>这是处理器在通电或复位后的工作模式。该模式使用16位长度的寄存器，而 16 位的最大值为 0xffff, 能够寻址最大 64k 的内存，为了更有效的使用内存，将内存按段进行划分，每段内存的地址通过 [段基址 : 段偏移] 的方式寻址，其计算方式如下:</p>
<blockquote>
<p>内存地址 = 段基址 * 16 + 段偏移</p>
</blockquote>
<p>因此构成了20位的物理地址长度，能够寻址的最大物理内存为 2^20B,  即能够寻址 1M 的内存。</p>
<p>由于该模式对指令的执行没有任何限制，因此程序可以直接访问硬件设备以及操作任意内存地址。</p>
<h4 id="Protected-mode"><a href="#Protected-mode" class="headerlink" title="Protected mode"></a>Protected mode</h4><p>该模式使用32位寄存器，可寻址的线性地址空间达到了4GB，通过 “Extended Physical Addressing” 使得可寻址的最大物理地址空间达到了 64GB(2^36)。</p>
<p>该模式提供了以下机制:</p>
<ul>
<li>段间的保护机制: 避免程序随意访问其他段的地址造成的系统崩溃</li>
<li>虚拟内存管理: 能够为应用提供逻辑上连续的线性地址空间</li>
<li>运行级别: 可以使系统和应用程序运行在不同的级别，是系统更健壮</li>
</ul>
<p>该模式通过提供“ Virtual-8086 Mode”子模式，使运行在该模式下的处理器依然能够运行实地址模式下的程序。</p>
<h4 id="System-management-mode-SMM"><a href="#System-management-mode-SMM" class="headerlink" title="System management mode (SMM)"></a>System management mode (SMM)</h4><p>该模式为操作系统实现平台相关的功能提供了一种透明的机制，如实现电源管理、系统安全等功能。</p>
<h3 id="Intel-64-架构"><a href="#Intel-64-架构" class="headerlink" title="Intel 64 架构"></a>Intel 64 架构</h3><p>即通常说的 x86_64/x64/amd64 架构。该架构添加了 IA-32e mode, 包含以下两种子模式:</p>
<h4 id="Compatibility-mode"><a href="#Compatibility-mode" class="headerlink" title="Compatibility mode"></a>Compatibility mode</h4><p>兼容模式为了使传统的16位或32位程序能够在不重新编译的情况下运行在64位操作系统下。</p>
<h4 id="64-bit-mode"><a href="#64-bit-mode" class="headerlink" title="64-bit mode"></a>64-bit mode</h4><p>该模式使用 64位 寄存器，可寻址的线性地址空间达到了 2^64B，可寻址的最大物理地址空间达到了 2^52B, 软件可以通过 CPUID 查询处理器支持的物理地址大小。</p>
<h2 id="寄存器"><a href="#寄存器" class="headerlink" title="寄存器"></a>寄存器</h2><table>
<thead>
<tr>
<th>8位</th>
<th>16位</th>
<th>32位</th>
<th>64位</th>
<th>主要作用</th>
</tr>
</thead>
<tbody><tr>
<td>AH/AL</td>
<td>AX(Accumulator)</td>
<td>EAX</td>
<td>RAX</td>
<td>用于返回值和累加器的操作数</td>
</tr>
<tr>
<td>BH/BL</td>
<td>BX(Base)</td>
<td>EBX</td>
<td>RBX</td>
<td>指向DS段数据的指针</td>
</tr>
<tr>
<td>CH/CL</td>
<td>CX(Counter)</td>
<td>ECX</td>
<td>RCX</td>
<td>用于字符串和循环操作计数</td>
</tr>
<tr>
<td>DH/DL</td>
<td>DX(Data)</td>
<td>EDX</td>
<td>RDX</td>
<td>I/O指针</td>
</tr>
<tr>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td></td>
<td>SI(Source Index)</td>
<td>ESI</td>
<td>RSI</td>
<td>DS寄存器指向的段数据的指针；字符串源操作数指针</td>
</tr>
<tr>
<td></td>
<td>DI(Destination Index)</td>
<td>EDI</td>
<td>RDI</td>
<td>ES寄存器指向的段数据的指针；字符串目的操作数指针</td>
</tr>
<tr>
<td></td>
<td>SP(Stack Pointer)</td>
<td>ESP</td>
<td>RSP</td>
<td>栈顶指针</td>
</tr>
<tr>
<td></td>
<td>BP(Base Pointer)</td>
<td>EBP</td>
<td>RBP</td>
<td>栈底指针</td>
</tr>
<tr>
<td></td>
<td></td>
<td></td>
<td>R8-R15</td>
<td>额外的通用</td>
</tr>
<tr>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td></td>
<td>CS(Code Segment)</td>
<td></td>
<td></td>
<td>指向代码段的起始地址</td>
</tr>
<tr>
<td></td>
<td>DS(Data Segment)</td>
<td></td>
<td></td>
<td>指向数据段的起始地址</td>
</tr>
<tr>
<td></td>
<td>SS(Stack Segment)</td>
<td></td>
<td></td>
<td>指向栈段的起始地址</td>
</tr>
<tr>
<td></td>
<td>ES(Extra Segment)</td>
<td></td>
<td></td>
<td>额外的段寄存器便于保存其他数据</td>
</tr>
<tr>
<td></td>
<td>FS</td>
<td></td>
<td></td>
<td>同ES</td>
</tr>
<tr>
<td></td>
<td>GS</td>
<td></td>
<td></td>
<td>同ES</td>
</tr>
<tr>
<td></td>
<td></td>
<td></td>
<td></td>
<td></td>
</tr>
<tr>
<td></td>
<td>IP(Instruction Pointer)</td>
<td>EIP</td>
<td>RIP</td>
<td>表示代码段中正在执行的指令偏移, CS:IP 用于确定当前指令的物理地址</td>
</tr>
<tr>
<td></td>
<td>FLAGS</td>
<td>EFLAGS</td>
<td>RFLAGS</td>
<td>用于存储指令的执行状态便于后续做相应的处理</td>
</tr>
</tbody></table>
<h2 id="Global-Descriptor-Table"><a href="#Global-Descriptor-Table" class="headerlink" title="Global Descriptor Table"></a>Global Descriptor Table</h2><p>GDT是由各种类型的段描述符实体组成的表，每个段描述符提供段的基地址以及访问权限、类型和使用信息。处理器在进入保护模式或64位模式之前必须加载GDT。</p>
<p>每个段描述符都有一个关联的段选择器，用于访问GDT/LDT中的段描述符。处理器通过段选择器能够知道当前段的基地址，再通过额外提供的相对于基地址的偏移，处理器就能够访问到任意的代码和数据以及栈， 前提是该段可以从当前处理器运行的特权级别(CPL)访问。</p>
<p>GDT结构如下：<br><img src="/blog/images/OS/Intel%E5%A4%84%E7%90%86%E5%99%A8%E6%9E%B6%E6%9E%84%E7%AE%80%E4%BB%8B/gdt.png" alt=""></p>
<p>段描述符结构如下:<br><img src="/blog/images/OS/Intel%E5%A4%84%E7%90%86%E5%99%A8%E6%9E%B6%E6%9E%84%E7%AE%80%E4%BB%8B/sd.png" alt=""></p>
<h2 id="参考连接"><a href="#参考连接" class="headerlink" title="参考连接"></a>参考连接</h2><ul>
<li><a href="https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html" target="_blank" rel="noopener">Intel® 64 and IA-32 Architectures</a></li>
<li><a href="https://developer.amd.com/resources/developer-guides-manuals/" target="_blank" rel="noopener">AMD64 Architecture</a></li>
</ul>

      
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